The present disclosure relates generally to computing devices and more particularly to dynamic core pool management of computing devices. Common types of computing devices are desktop computers and server systems. Designers of computing devices, like next-generation servers, spend considerable amounts of time analyzing and designing system-level power management. Without system-level power management, the computing devices are not able to stay within design constraints and other limitations, such as the limitations imposed by data center power and cooling systems. In addition, current system-level power management elements have inefficiencies. Such inefficiencies are important, given that energy is becoming an increasingly expensive commodity. Lawmakers and consumers are demanding more power-efficient computing devices, as well as power-manageable computing devices.
In many modern computing devices processors consume relatively large quantities power. As processors consume larger and larger quantities of power, processors correspondingly generate more and more heat. In other words, processor design trends are improving performance but also increasing power consumption and heat density. In server systems, the pool of processors generates most of the heat of the systems. So controlling the power consumed by processors, especially when the system load is relatively low, often proves to be important when achieving energy efficiency.
Current solutions for controlling processor power in computing devices generally fall into one of three categories. The first category comprises low-level gating techniques that detect one or more portions of a processor are idle. Low-level gating mechanisms reduce or turn off power to the idle circuits to conserve energy.
A second category of controlling power in a computing device comprises processor or clock throttling. Throttling injects “dead” cycles into processor pipelines or in the processor clock to reduce the activity level of the processor. For multiple-core processors, throttling is generally applied at the level of individual processor cores. This technique offers a quick way to reduce power, but the amount of power reduction from throttling is limited. Plus, throttling generally has a negative impact on processor performance.
The third category comprises processor scaling. Dynamic voltage scaling and dynamic frequency scaling (DVFS) tend to be effective over a somewhat limited range. The range of using DVFS is bounded due to frequency and voltage requirements of the processors in a system.